Dynamic on-Resistance in GaN-on-Si HEMTs: Origins, Dependencies, and Future Characterization Frameworks

Gallium nitride high-electron-mobility transistors (GaN HEMTs) exhibit dynamic ON-resistance (dR on ), where the ON-resistance immediately after turn-ON is higher than the dc value at the same junction temperature. A proliferation of recent literature reportsdR on , with some publishing an eight times increase in conduction losses and others finding that the problem is nonexistent. This variation can be largely attributed to the standardized double-pulse-test (DPT) method, which does not specify the blocking time and will ignore any effects that accumulate over multiple switching cycles. With no consistent measurements, designers are left without an accurate conduction loss estimate in converters with GaN HEMTs. We discuss the underlying causes of charge trapping to find the key influences over dR on , and show that the DPT technique gives invalid results. Our measurements validate that each operating parameter must be independently controlled and that only steady-state dR on measurements will predict in situ performance. For the commercial GaN HEMT tested in this letter, the worst-case dR on is nearly two times higher than the dc resistance at the same temperature, confirming that accurate dR on characterization remains critical to predicting converter characteristics. Finally, we provide a reporting framework for GaN HEMT manufacturers and methods to estimate conduction losses in converters with GaN HEMTs.