Optimized Nanoscale Adder-Subtractor Design Architectures Utilizing Quantum Dot Cellular Automata

Abstract Quantum dot cellular automata (QCA) is a novel technology with the potential to address the limitations of standard CMOS technology particularly as we approach physical and practical limits in traditional transistor miniaturization. QCA provides multiple benefits including ultralow energy dissipation, improved computational performance, high device integration density, scalability, resilience, and inherent parallel processing capabilities. Adders and subtractors are vital components in digital systems and have been developed using QCA technology for various mathematical functions. However, antecedent implementations of QCA based adders and subtractors have struggled with high cell count, elevated energy dissipation, increased complexity, and robustness. This paper presents an efficient design of adder-subtractor based on novel 3-input XOR gate. The proposed designs achieve reduction in cell complexity of 5%, 27%, and 11% for adder, subtractor, and adder-subtractor circuits compared to earlier counterparts. The functional integrity of the drafted layouts is validated through simulations performed using QCAdesigner 2.0.3 simulator. The energy dissipation profiling was conducted using QCADesigner-E tool. The examination of energy analysis indicates that the proposed designs exhibit energy efficiencies of 7%, 25%, and 10% for the adder, subtractor, and hybrid adder-subtractor relative to the most optimized alternatives available. For adder, subtractor, and adder-subtractor designs, respectively.