Response of interface traps during high-temperature anneals (MOSFETs)

Isochronal-annealing measurements were performed on n-channel Si-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) to determine the temperature at which interface traps anneal following exposure to 10-keV X-rays. All five of the processes sampled exhibited annealing by 300 degrees C, although this annealing was generally preceded by an increase in the number of interface traps (N/sub IT/) at lower temperatures. In particular, N/sub IT/ for two of the processes increased at 100 degrees C. Additional annealing experiments at 100 degrees C for a week are consistent with these results. The implications of these results for high-temperature accelerated-annealing rebound testing are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>