Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias

This paper discourses the variations in methods of fabrication and modeling of Through-Silicon Vias (TSVs) in chronological order. Three-dimensional (3D) integration is an emerging technology that forms multi-functioning high-performance ICs by vertically stacking of disparate technologies and components altogether. TSV has the potential to become an essential component in integration and packaging of 3D ICs. However, the limited information about TSV technologies brings the challenge in selecting the appropriate filler material of TSVs. This review paper overviews the copper (Cu)- and carbon nanotube (CNT)-based TSVs and their pros and cons to be established as suitable filler material for 3D TSVs. The equivalent electrical models of both Cu and CNT-based TSVs are discussed addressing their advantages and disadvantage to reason out the most promising method for the modeling of TSVs.