Suppression of Humidity‐Induced Drain‐Induced Barrier Lowering Degradation in a‐Si:H Thin‐Film Transistors via Structural Field‐Dispersion Engineering

This study investigates structural engineering to suppress humidity‐induced drain‐induced barrier lowering (DIBL) degradation in back‐channel‐etched (BCE) amorphous silicon (a‐Si:H) thin‐film transistors (TFTs). At 80% RH, polar H 2 O infiltration significantly exacerbates DIBL instability. We comparatively analyzed standard (STD), thin‐channel (Thin‐CH), and thickened i‐layer (Thick‐i) architectures. Thick‐i achieved a 70% DIBL reduction (from 93.0 to 29.1 mV/V). While Thin‐CH enhances vertical gate control, Thick‐i provides superior geometric shielding by elongating electric field paths. TCAD simulations confirm that Thick‐i reduces transverse field strength by 30% through geometric field dispersion and electrostatic decoupling. This high‐aspect‐ratio design offers a robust, cost‐effective strategy to enhance TFT reliability for high‐humidity display applications. The optimized fabrication process leverages high film homogeneity to ensure baseline structural reproducibility, while the field‐dispersion design successfully retards long‐term environmental aging effects under high humidity.