A low-offset double-tail dynamic comparator for low-power applications

The proposed double-tail dynamic comparator (DTDC) architecture effectively reduces power consumption and offset voltage, making it suitable for energy-constrained, high-speed analogue applications. Including PMOS switching transistors MR4 and MR5 enhances latch activation speed while minimising energy usage in low-voltage environments. These switching transistors’ sources are connected to VDD to provide a high overdrive voltage that lowers the latch time constant and speeds up the comparator by enabling a quick high-current path during regeneration. Simulation in 90 nm CMOS technology demonstrates notable performance improvements over prior designs in both power efficiency and offset voltage. Achieving a 64.48% power reduction and 68.25% offset improvement shows the designs competitiveness in low-power analogue circuits. The measured slew rate and delay indicate strong potential for integration into low-power, high-frequency mixed-signal systems.