Base current relaxation transient in reverse emitter-base bias stressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO/sub 2//Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of /spl sim/10/sup -3/ s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements.