Integration of self-assembled carbon nanotube transistors: statistics and gate engineering at the wafer scale

We present a full process based on chemical vapour deposition that allows fabrication and integration at the wafer scale of carbon-nanotube-based field effect transistors. We make a statistical analysis of the integration yield that allows assessment of the parameter fluctuations of the titanium–nanotube contact obtained by self-assembly. This procedure is applied to raw devices without post-process. Statistics at the wafer scale reveal the respective role of semiconducting and metallic connected nanotubes and show that connection yields up to 86% can be reached. For large scale device integration, our process has to implement both wafer-scale self-assembly of the nanotubes and high transistor performances. In order to address this last issue, a gate engineering process has been investigated. We present the improvements obtained using low and high κ dielectrics for the gate oxide.