A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n/sup +/ source-drain implantation, Be and Be/P p/sup +/ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices fabricated with this approach exhibited a maximum transconductance of 140 mS/mm, which is believed to be the highest reported for InP JFETs.>
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Boos et al. (1989) studied this question.
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