We propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization-Contraction) technique, to screen out the basal plane dislocations (BPDs) which might cause the forward voltage degradation of SiC devices. Since the method can be adopted at the epi wafer receiving inspection process in early stage of production line, it may replace the very time-consuming so-called "burn-in" operation currently utilized in some device manufacturers.
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Takano et al. (2022) studied this question.
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