The linear RC delay model is commonly used in timing simulators for MOS digital circuits. Most simulators only handle tree networks, not arbitrary networks. More precisely, these simulators treat all networks as if they were trees. Currently, the only alternative is to invert the node-conductance matrix of the RC network numerically. Upper and lower bounds on signal delays in general RC networks are derived. The idea is to bound (element-wise) the inverse of the node-conductance matrix of the network, and use these bounding matrices in formulas for estimating signal delays in RC networks. Evaluating the bounds requires finding the least-resistance paths and the maximum cut between the input mode and the rest of the nodes in the network. For tree networks, the bounds coincide and are the same as those found by using a method due to P. Penfield, et al. (1970).>
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Chan et al. (1989) studied this question.
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