A 1-V operating 256-kb full-CMOS SRAM

A 1-V operating 256-kb full-CMOS SRAM to be used in 1.5-V battery-based applications is presented. A reference word line and address transition detection (ATD) are used as timing control techniques to achieve adjustable timing of critical signals with a 1.5-V battery. The key circuit of the pulse sequence block is the ATD pulse generator circuit. The authors use a newly modified Schmitt trigger delay circuit. To reduce supply line noise in the chip, they needed to lower the peak of bit-line charge-up current. This was done by applying a divided word-line technique and a newly adopted staggered bit-line equalizing pulse technique. The design used a single-polysilicon and double-aluminum process with a full-CMOS memory cell of 8.5 mu m*12.8 mu m. The chip size is 6.0 mm*9.0 mm.>