Fabrication of co-planar metal-insulator-metal solid state nanojunctions down to 5 nm

This is the authors' abstract. We don't add key points for this paper.

An optimised process is presented to fabricate co-planar metal-insulator-metal nanojunctions down to an inter-electrode distance of 5 nm. Simulation of the e-beam insulation of the PMMA/SiO2/Si interface is used to optimise the PMMA resist thickness and the exposure strategy. The process was well stabilised to provide a full statistical analysis of the number of nanojunctions produced per wafer. A 10% throughput was reached for 5 nm giving a mass production of about 100 nanojunctions per 2 inches wafer all equipped with their interconnection pads.