Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays

Recently a prototype of complementary resistive switches has been proposed to solve the sneak-path problem in passive crossbar memory arrays. To further evaluate the potential of this novel cell structure for practical applications, we present a modeling analysis to capture its switching dynamics and analyze its unique read/write schemes. The model is corroborated by experimental data. We found a trade-off between the read voltage window and write voltage window. The constraint from avoiding disturbance on unselected cells is critical for proper functionality, which in turn limits the writing speed.