A 300 kbit bubble memory chip with planar structure

A 300 kbit bubble memory chip has been designed based on 3 μm bubble technology. Nominal circuit period is 14 μm and chip size is 9.8 mm×9.6 mm. A gap-tolerant design is fully employed, such as, asymmetric half-disk propagation pattern, half-disk transfer gate, a novel asymmetric-chevron stretcher, etc. The chip is fabricated using a new planar process solving step-coverage problems to achieve good process yield. A typical bias field margin of 18 Oe is obtained at 55 Oe with a triangular wave drive.