Novel nanoscale device architecture to reduce leakage currents in logic circuits: a quantum-mechanical study

In this paper we investigate the reduction in leakage components of a fully depleted (FD) nano-scale double-gate (DG) MOSFET architecture. We have developed a numerical model for a parallel connected hetero-material double-gate (PCHEM-DG) MOSFET followed by gate-controlled band-to-band tunnelling leakage and gate leakage currents in a device having a gate length of 10 nm, and we have observed a reduction in the leakage components compared to bulk MOSFETs. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with a MINIMOS 6.0 standard device simulator for the purpose of validating the results. A dramatic increase of the gate leakage and band-to-band tunnelling (BTBT) leakage in nanoscale devices drastically increases the total leakage power in a logic circuit. The PCHEM-DG MOSFET proposes to reduce this power dissipation. This work provides a simple and intuitive method for lowering leakage currents which could be very salutary for future nano-scale device technologies.