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Simulation study demonstrates simplified check-node operations in low-density parity-check decoders, indicating reduced wiring complexity in integrated circuit hardware.
This letter presents a heuristic technique for simplifying the parity-check node operation in a relaxed min-sum iterative decoder. The proposed decoder eliminates the second-minimum computation in check nodes, which allows broadcasting the same output to all neighboring variable nodes to alleviate routing problem in VLSI implementations of low-density parity check (LDPC) decoders. The second-minimum, when required, is emulated by adding an offset to the first-minimum. The proposed relaxed decoder also uses a relaxation factor equal to 0.5 to simplify variable nodes. Simulation results for two LDPC codes show the proposed decoding algorithm with only 4-bit quantization closely matches the performance of floating-point normalized/offset min-sum and sum-product decoders in the waterfall region.
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Hemati et al. (2016) studied this question.
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