Vyges Loom: A Shared Data-Spine Architecture for Open Sign-Off and Physical Design Optimization

Open-source EDA can now carry a design from RTL toward GDSII — synthesis, place-and-route, DRC, SPICE — but sign-off-quality timing closure, and the optimization that closes it, have remained the preserve of proprietary tools. We present Vyges Loom, an open (Apache-2.0) suite that substantially narrows that gap as a software architecture rather than a bundle: one set of format parsers and a common in-memory data model — vyges-loom for the electrical/timing domain and a memory-safe vyges-layout / vyges-geom stack for geometry — over which a family of sign-off, optimization, and verification engines compose through declarative job files and standard artifacts (Liberty, SPEF), with no glue scripts and no silent copy-drift. Written in Rust, it is memory-safe, GC-free, and deterministic, and one code base runs natively across x86_64, Arm64, and Apple Silicon. A cone-localized incremental timing engine makes the optimizers' speculative inner loop practical — the same timer that signs a design off is what the optimizers act on. We correlate the engines against the golden open tools on sky130 (within ~1–3% of OpenSTA on timing, ≈0.997 vs OpenRCX on parasitics, exact layout-vs-schematic vs Magic, thermal hotspot in agreement with HotSpot) and demonstrate end-to-end optimization on an OpenROAD-routed block. Loom makes sign-off-quality, foundry-format, CI-native sign-off and optimization reproducible and accessible on open process nodes.