High- k insulators are currently considered for SiO 2 replacement as gate dielectrics in sub-100 nm complementary metal-oxide-semiconductor (CMOS) technology nodes. The use of double-layer high- k stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the programming speed. In this paper, the influence of the high- k parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low- k /high- k dielectric stacks and confirm the theoretical results based on our experimental data.
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Govoreanu et al. (2003) studied this question.