Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation

Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VTanalog decoding techniques. Novel sub-VTdigital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VTimplementation is predicted to offer 29× gain in power consumption for a (3,6) low-density parity-check decoder of lengthN= 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design.