Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link

High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-Jc(4.5 and 20kA/cm²) fabrication process.