EX-DRIVE: An Execution Driven Functional Verification Flow

In EDA industry, design-under-test (DUT) is a pre-silicon digital design which is still undergoing testing phase. We perform functional-verification of a DUT to verify whether the DUT conforms to the specifications. Functional verification has been pre-dominantly performed through simulation of a DUT. However, their execution speed rapidly degrades when DUT size reaches 100 million gates. This increase in design complexity then results in almost doubling the verification effort. The increasing design and verification space bring about the need for random dynamic simulation, using which only the typical behaviors, and not all possible behaviors of a chip, can be verified in a time bound simulation run. To overcome this bottleneck, the EDA industry is increasingly adopting “hardware-accelerated simulation platforms,” which are classified as simulation-accelerators, emulators and FPGA prototypes. These still does not address the state-space problem effectively as all these platforms still work in the cycle-driven or event-driven mode and calls for a huge design porting effort to the native development environment. The need of the hour is a simulator that needs to be design-aware enough to partition and map huge data-flow graphs (DFGs) of scientific applications at each abstraction level of verification and schedule it for simulation. In this paper, we present a novel approach for dynamic pre-silicon verification, called EXDRIVE (execution-driven functional verification methodology). It addresses the state-space explosion problem in verification by hostin a variety of partitioning and mapping algorithms. We show that the proposed functional-verificatio flow achieves significant improvement in verification performance over industry standard simulator and emulation platforms.