A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 μA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 μs/phase, differential current of 150 μA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.
No takes yet. Share an insight, caveat, or question.
Biederman et al. (2015) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: