The effects of MOS transistor mismatch upon sense-amplifier yield in synchronous static RAM memories is investigated. The matching characteristics of the two transistor layout styles are compared, a general formula is derived for calculating the statistical likelihood of the sense amplifier failing to read correct data given transistor size and input differential voltage, recommendations are made for optimizing size/speed/reliability trade-offs.
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Lovett et al. (2000) studied this question.
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