A review of high fan-in circuit design in contemporary logic technologies is presented. This is followed by a description of BiNMOS circuit structures which allow the construction of large fan-in, logical AND or OR functions. The first is a dynamic design, while the second is static. Application of the former in a 3.3 V, 100 MHz, implementation of the Pentium Microprocessor on a 0.6 /spl mu/m BiNMOS process is described, while application of the latter in a 0.35 /spl mu/m BiNMOS implementation is presented. Power and reliability considerations such as bipolar junction transistors (BJT), reverse V/sub bc/, and MOS hot electron protection are included.
No takes yet. Share an insight, caveat, or question.
Clark et al. (1996) studied this question.
Synapse has enriched 3 closely related papers on similar clinical questions. Consider them for comparative context: