A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test

An experimental 576 K BiCMOS emitter-coupled-logic (ECL)-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1 K on-chip logic gates to assist characterization, wafer testing, and package testing. The I/O is also transistor-transistor-logic (TTL) programmable with the first-metal mask.>