Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems

Among timing-error-detecting registers, the transition-detector-based error-detecting latch (TD-EDL) is regarded as the most lightweight design. To realize a truly variation-resilient system, a TD-EDL should be designed to be robust across all process/voltage/temperature (PVT) corners. In particular, its detection window deviation must be carefully compensated for an accurate detection. It must also be small, as well as power and energy efficient, to prevent excessive overheads. This paper carefully redesigned several conventional TDs in 28-nm CMOS process, and postlayout simulations were performed to examine the pros and cons of the TDs. According to the characteristics of each TD, the transistor sizing methods were explored to achieve PVT-variation-aware designs. The redesigned TDs were then used to construct TD-EDLs, for which the causes of detection window deviation were examined and improved upon. The timing characteristics that affect the correct function and appropriate responses were discussed, and the area overhead, timing performance, power consumption, and voltage scalability of the TD-EDLs were evaluated and compared.