Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion

In this paper, we study the full-chp interconnect power model-ing.,We show that repeater,insertion is no longer sufficient to achievethe target frequencies specified hy ITRS, and develop con-current repeater and FF insertion schemes. Considering struc-tural. interconnects, layer assignment and concurrent repeater and FF insertion for delay specification, we develop a cycle-accurate microarchitecture-level interconnect power simulation'. The sim-ulation reduces the over-estimation by'up to 2.46X compared to power estimation hasedon purelystochasticinterconnects and fixed switching factor. Furthermore, we show that interconnect pipelin-ing his a lower IPC but can improve throughput by up to 2.03X. This indicates that the traditional design flow optimizing IPC and clock frequency separarely may no longer be valid. 1.