An ever-increasing need is present for portable devices with less power consumption, hence the need for low-power consumption and small-sized memory systems. The research introduces ultra-low-power Static Random-Access Memory (SRAM) memory cell architectures using Carbon Nanotube Field Effect Transistors (CNTFETs) along with Gate Diffusion Input (GDI) logic for applications at the nanoelectronics level. Four types of SRAM cell architectures, including 6T, 5T, 4T and 3T, have been designed in conjunction with compact 10-transistor GDI decoders to provide scalable 4 × 4 and 16 × 16 SRAMs. This paper proposes an architecture to decrease the ii. Informed Consentnumber of transistors, energy consumption, and access time while assuring reliable memory functioning. The simulations carried out with the Stanford 32 nm CNTFET model prove that the 3T SRAM cell exhibits superior performance with minimum energy consumption of 1.75 µW and access delay of 8.58 ps. GDI decoders reduced power consumption and the number of transistors used compared to other types of decoder logics. Besides maintaining efficient power-delay trade-offs, larger arrays confirmed the design’s scalability. Moreover, the energy dissipation and delay of the 16 × 16 SRAM architecture are low. Comparing the proposed research with recent developments in SRAM shows superior power savings and fewer transistors in our design.
Saleem et al. (Wed,) studied this question.