The impact of NiPt thickness scaling on total resistance is investigated using short-channel(Lg = 40\ nm)nm high- k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (“planar single-gate thin-body FD SOI FET”) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a> 2×(NFET) and> 6×(PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs.
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Akarvardar et al. (2012) studied this question.
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