FPGA implementation of a full HD real-time HEVC main profile decoder

High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 % compared to H.264/MPEG-4 AVC high profile, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications - make implementing encoders and decoders a challenging task. A few software based implementations on DSPs and general purpose CPUs are known from the literature which suffer from real-time constraints, power dissipation and hardware costs of these systems. In this paper a pure hardware implementation of a Main Profile H.265/MPEG-HEVC Full HD capable decoder is presented solving both real-time and power constraints respectively. As a first implementation approach a state-of-the-art FPGA technology is chosen as a prototyping platform. This design can be used as a starting point for an ASIC implementation.