Enhanced yield and reliability through process improvements, leading to a manufacturable process for a full-bit functional 8 Mbit one transitor–one capacitor (1T–1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm, 5 lm Cu/fluorosilicate glass (FSG) interconnect complementary metal oxide semiconductor (CMOS) logic process, are described. Higher signal margins are further enabled by the single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements. Retention tests on wafers with signal margins above a threshold value for screen show no bit fails for bakes extending up to 1000 h, suggesting retention lifetimes of more than 10 years at 85 °C. Using the qualified process reported in this paper, commercial products are being routinely produced in our fabrication facilities.
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Udayakumar et al. (2008) studied this question.
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