The architecture and performances of a multilevel driver for pulse amplitude modulation (PAM) formats, designed and fabricated in 0.7 µm InP double‐heterojunction bipolar transistor technology, are reported. The driver part is based on a power‐DAC architecture which is integrated with the multiplexing stage composed of three 2:1 selectors. Up to 100 GS/s operation was validated and PAM‐2, ‐4, ‐8 signals with high amplitude were measured. In particular, PAM‐4 at 84 GBd and PAM‐8 at 64 GBd operation was demonstrated with, respectively, a 3.7 and 4 V pp differential output signal. This compact driver circuit is characterised by the highest merit factor in terms of high amplitude and the transmission capacity for an electronically generated multilevel signal.
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Konczykowska et al. (2015) studied this question.
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