An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Traditional digital systems employ independent loops to control supply voltage (Vdd) and clock frequency (fclk). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets Vddto a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant Vddfluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful Vddguardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts fclkto Vddand T variations, requiring minimal guardbands. UniCaP absorbs Vddcontrol into the clock regulation loop, using it to adjust fclkand lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive Vddguardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6-1.0-V Cortex-M0 microprocessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average Vdd guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40-55 mV.