A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage (Vdd) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature andVddvariation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce requiredVddguardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressiveVddmargin reduction, and continuousVddscalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16%Vddreduction corresponding to a 94%Vddmargin recovery or an equivalent3.2×increase in the operating clock frequency (fclk).