Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

This paper presents novel processor architecture for HP-processor with MRAM/SRAM-based hybrid cache memory. By simulations of HP-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM [H. Yoda, et al., Current Appl. Phys. 10, e87 (2010)] can be reduced by 50.2% without any degradation of operation speed. This is the first report on effectively decreasing total power of HP-processors with no degradation of performance using magnetic memory. The presented architecture will be the first step to realize the next generation “normally-off computers.”