Advances in correlative microscopy and next-generation devices toward the CHIPS Act

The bipartisan CHIPS and Science Act of 2022 and subsequent guidelines offered by the National Institute of Standards and Technology emphasize the role of advanced metrology capabilities to play a vital role in the manufacturing, characterization, and integration of new semiconductor materials and devices. As the complexity of the fabrication process increases and characteristic dimensions of devices decrease, the community is faced with the extraordinary challenge of probing at scale their thermal, electrical, mechanical, chemical, and optical properties. Accessing this information remains a key endeavor to enable validation and verification of a device's functionality, yield, and ultimately, its economic viability in future semiconductor industry innovations. Therefore, in recent years, the idea of correlating multiple analytical microscopy techniques, often termed correlative microscopy, has emerged as a promising approach for the characterization of novel materials and process module optimization. One important area of research to improve our metrology capabilities is the hybridization of multiple analysis techniques into a single platform. Here, we review the efforts in applying multiple microscopy methods to a single area of interest to achieve analysis across a broader range of magnifications than any single technique can provide. Scanning electron microscopy and atomic force microscopy exemplify this synergistic approach, allowing researchers to explore mechanical, electrical, and chemical properties at the nanoscale. Such detailed insights are crucial for understanding nanoscale mechanisms like thermal dissipation, carrier mobility, and magnetic susceptibility, used to predict performance and fault tolerance thresholds in novel device applications. We demonstrate their impact on semiconductor materials research fields, such as the study of thin films, nanostructures, two-dimensional (2D) materials, and packaging for heterogeneous integration. This review will emphasize laboratory-based metrology research rather than in-line wafer-scale chip manufacturing, although some of the conclusions can be directly extended.