A 102–129-GHz 39-dB Gain 8.4-dB Noise Figure I/Q Receiver Frontend in 28-nm CMOS

An F-band in-phase/quadrature-phase (I/Q) receiver front-end in 28-nm CMOS for chip-to-chip communication is presented. The receiver consists of a capacitively neutralized differential low-noise amplifier (LNA) chain, a passive ring mixer, zero-IF drivers, and a novel tunable transformer-based quadrature splitter. This paper discusses the effect of capacitive neutralization on common-mode stability, matching losses, and the noise performance of a differential pair. A technique for gain and noise-figure optimization by core sizing and partial neutralization is presented. The receiver exhibits a gain of 39 dB, a 3-dB RF bandwidth of 27 GHz, a noise figure between 8.4 and 10.4 dB, and a P1 dB of 3.2 dBm. The receiver front-end consumes 18 mW from a 1.0-V supply and the baseband I and Q buffers consume a total of 33 mW from a 1.5-V supply. A breakout of the LNA shows a measured gain of 21 dB, a noise figure of 8.0-9.4 dB, with a gain power efficiency of 1.2 dB/mW around 125 GHz.