Design and Simulation of a Fast-Locking 4.4 GHz Ring Oscillator PLL for C-Band Weather Radar

This work reports a 4.4 GHz integer-N charge-pump PLL targeting C-band weather radar frequency synthesis, designed and simulated in 90 nm CMOS with a 1.8 V supply. The oscillator is a nine-stage current-starved ring structure with a measured tuning sensitivity of 1.0 GHz/V. Frequency division by 32 through a five-stage TSPC chain brings the output back to the 137.5 MHz reference. Starting from a cold initial control voltage of 0.7 V, the loop pulls up and settles at 1.176 V in 4 µs fast enough for event-triggered radar activation without meaningful data loss. Locked output shows −85 dBc/Hz phase noise at 1 MHz offset, 3.3 ps RMS jitter, and ±0.77% frequency stability. Each circuit blocks like the ring VCO, TSPC divider chain, tri-state PFD, current-mirror charge pump, and passive RC loop filter is described, with attention to the tradeoffs between lock speed and phase noise that define inductor-free PLL design at C-band.