ARMOR: Robust and Efficient CNN-Based S AR ATR through Mo del-Ha r dware Co-Design

Convolutional Neural Networks (CNNs) have achieved state-of-the-art accuracy in Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR). However, their high computational cost, latency, and memory footprint make deployment challenging on resource-constrained platforms such as small satellites. While adversarial robustness is critical for real-world SAR ATR, it is often overlooked in system-level optimizations. Achieving both robustness and inference efficiency requires a unified framework that considers adversarially trained models together with hardware constraints. In this paper, we present a model-hardware co-design framework for CNN-based SAR ATR that integrates robustness-preserving model compression with FPGA accelerator design. The compression stage includes hardware-guided structured pruning, where a hardware performance model derived from the FPGA design predicts the pruning impact on latency and resource usage. This enables the generation of Pareto-optimal models that improve hardware efficiency under user-defined objectives while maintaining adversarial robustness within a predefined tolerance. We design an FPGA accelerator with channel-aware processing element (PE) allocation that supports both fully pipelined streaming and temporal resource-reuse architectures. An automated design generation flow efficiently maps the compressed models to optimized FPGA implementations. Experiments on the widely used MSTAR and FUSAR-Ship datasets across three CNN architectures show that our framework produces models up to 18.3 \(×\) smaller with 3.1 \(×\) fewer MACs while preserving robustness. Our FPGA implementation achieves up to 68.1 \(×\) (6.4 \(×\) ) lower inference latency and up to 169.7 \(×\) (33.2 \(×\) ) better energy efficiency compared to CPU (GPU) baselines, demonstrating the effectiveness of the proposed co-design framework for robust and efficient SAR ATR on FPGA platforms.