A standardized approach to characterize hysteresis in 2D-materials-based transistors for stability benchmarking and performance projection

The hysteresis observed in the transfer characteristics of emerging transistors based on 2D-materials is widely accepted as an important metric related to the device quality. However, the specifics of hysteresis characterization measurements are rarely given, and its mechanistic understanding remains fragmentary. Here, we provide a comprehensive theoretical analysis of the dominant mechanisms contributing to hysteresis: charge trapping by defects from the channel or the gate, the drift of mobile charges, and eventually ferroelectricity. We suggest methods to experimentally distinguish between these phenomena and propose a standardized hysteresis measurement scheme to establish the hysteresis as a comparable metric for the assessment of device stability. Our standardized scheme ensures that hysteresis data can be effectively compared across different technologies and, most importantly, provides a means to extrapolate data obtained on thicker prototypes to subnanometer equivalent oxide thicknesses. This facilitates the systematic benchmarking of insulator/channel combinations in terms of stability, which thereby enables the screening of material systems for more stable and reliable 2D-material-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Hysteresis in the transfer characteristics of 2D transistors is considered an important metric to evaluate their performance, but its characterization process is often inconsistent among different studies. Here, the authors propose a standardized scheme to measure and analyze hysteresis in different 2D devices, facilitating systematic comparisons and performance projections.