This paper presents a parallel binary NOR-gate adder circuit with carry completion detection. The circuit consists of identical one-position adders. The number of NOR gates in the adder carry line is equal to the number of one-position adders, i.e., half that of any other known solution consisting of one-position adders. The solution is very economical. A one-position adder contains only six NOR gates, and the detection circuit has approximately half a NOR gate for every adder position.
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Majerski et al. (1967) studied this question.
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