Hysteresis in the transfer characteristics of MoS ₂ transistors

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS 2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS 2 /SiO 2 interface. We conclude that intrinsic defects in MoS 2 , such as S vacancies, which result in effective positive charge trapping, play an important role, besides H 2 O and O 2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.