Hybrid-lithography fabrication of sub-micron device structure for resistive material evaluation in memory applications

Resistive random-access memory is a leading candidate for next-generation non-volatile memory and neuromorphic computing, but fabricating statistically meaningful device populations at sub-micron dimensions remains challenging in academic settings. We present a hybrid-lithography test-vehicle platform combining photolithography for large-scale interconnects with electron-beam lithography for sub-micron patterning, achieving overlay errors below 30 nm while reducing write time by ~ 4 × through optimized alignment strategies for the chiplet layouts studied here. The standardized 20 × 20 mm coupon architecture, subdivided into 2 × 2 mm chiplets housing 32-bit and 128-bit memory arrays, supports multiple material stacks across substrates. NiO-based metal–insulator–metal devices fabricated at 500 nm and 3 µm both exhibit stable unipolar resistive switching with ON/OFF ratios ~ 10 3 , comparable SET/RESET voltage distributions, and filamentary conduction behavior. This platform provides a scalable, reproducible foundation for BEOL-compatible resistive datasets and standardized benchmarking of emerging switching materials can be built in academic environments.