Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size

A spatially discrete grain-boundary model for characterizing polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) is developed. This model was formulated for an interface state localized at the grain boundary. Threshold voltage (Vth) variation was analyzed using the model by changing the trap density and the location and number of grain boundaries in the poly-Si channel. The Vth shifts were found to be linearly dependent on the trap density (NGB) at the grain boundary and almost independent of the boundary location. The dependence of Vth on NGB was 0.15 V per trap density of 1012 cm−2 in long-gate TFTs. Since grain formation in the poly-Si channel is not controllable (it tends to be random), the threshold-voltage shift (ΔVth) predicted by the simulation will appear as statistical fluctuation in device fabrication. Simulation of the Vth fluctuation ranges showed that ΔVth increases with a decrease in channel length and will exceed 0.2 V in TFTs with a channel length of 1 μm or less when there is one grain boundary in the channel region and the trap density is 1012 cm−2. However, adding a moderately doped p region near the source in an n-channel TFT will suppress threshold-voltage fluctuation, even when the grain formation is uncontrollable, as we have theoretically demonstrated through simulation.