A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2/spl times/3.1 mm/sup 2/ in a 0.7 /spl mu/m CMOS process. Several circuit techniques used in this design together with experimental results are presented.