Miniaturization of Josephson logic circuits

The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 × 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates, Some suggestions are given for further improvements.