Multi-Gb/s operation of flipped chip MVTL circuits

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRW's foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.