Modeling of the Threshold Voltage in Strained Si/Si1 - x Geₓ/Si1 - yGey(x ≥ y) CMOS Architectures

In this paper, an analytical model of threshold voltage for globally strained Si/SiGe CMOS devices using a dual channel architecture is proposed. Since band parameters modify , they are calculated and generalized for different Ge contents in a film grown on relaxed virtual substrates . A model for predicting is then developed by considering device geometry and material properties, including band parameters, permittivity, and channel and substrate doping concentrations. lowering due to short-channel effects is included by incorporating a voltage-doping transformation. Accuracy of the model is verified by comparing the model with the results of technology computer-aided design simulations and experiments. The model provides a physical insight for the variation of for both n- and p-MOSFETs in a dual-channel architecture, and it can be generalized to be applicable to single-channel devices as well.