Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation.